RoCE is a protocol where a chunk of memory (e.g., random access memory (RAM)) is transferred over a wire transparently to a central processing unit (CPU) as a direct interaction between the memory and a network interface card (NIC). RoCE expects a very low latency network since it is a Direct Memory Access (DMA) (i.e., does not require the use of the CPU) and is highly sensitive to data loss. For example, even a low rate of loss can still lead to a livelock where the communication link is fully utilized, but because of loss, the chunk of memory cannot be recovered at the receiver.
Currently, there are two RoCE versions: RoCE v1 and RoCE v2. RoCE v1 is an Ethernet link layer protocol and allows communication between any two hosts in the same Ethernet broadcast domain. RoCE v2 (and future version RoCE v4) is an internet layer protocol which means that RoCE v2 packets can be routed through a network. However, adapting RoCE v1 or RoCE v2 to include a wireless link is difficult since these protocols require quasi deterministic transport and very low loss.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.